This invention relates to performing floating-point arithmetic operations in integrated circuits and, more particularly, to dynamic bit extension and shifting techniques for floating-point operations.
Floating-point operations are usually implemented in accordance with the IEEE754 standard, which defines a floating-point number as having a sign, a mantissa, and an exponent, in which the mantissa is required to be normalized at all times because the standard implies a leading “1.” However, performing normalization can be expensive in terms of circuit area and operational latency. Some floating-point operations also require that the floating-point number operands be manipulated as part of a floating-point operation. For example, floating-point addition and subtraction require that the mantissas of the floating-point number operands be aligned in such a way that the exponents of the floating-point number operands are equal.
Situations frequently arise where several floating-point operations are executed sequentially (e.g. in an adder tree). Such sequentially executed operations require the normalization of the mantissa produced by a first adder stage followed by the alignment of the mantissas entering a second adder stage.